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[OS Develop] FIFO

Description: fifo.v verilog实现的先进先出存储器-fifo.vverilog realize the FIFO memory
Platform: | Size: 2048 | Author: patrick | Hits:

[VHDL-FPGA-Verilog] an_dcfifo_top_restored

Description: alteral FPGA VERILOG 利用 ROM DCFIFO 和RAM 实现高速到低速时钟域的数据传输 ，值得学习。-alteral FPGA VERILOG using ROM DCFIFO and RAM to realize high-speed low-speed clock domain data transfer, it is worth learning.
Platform: | Size: 928768 | Author: alison | Hits:

[VHDL-FPGA-Verilog] DW8051

Description: Verilog版的C51核(DW8051)-Verilog version of the C51 core (DW8051)
Platform: | Size: 67584 | Author: | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 采用VHDL语言设计一个4通道的数据采集控制模块。系统的功能描述如下： 1.系统主时钟为100 MHz。 2.数据为16位-数据线上连续2次00FF后数据传输开始。 3.系统内部总线宽度为8位。 4.共有4个通道（ch1、ch2、ch3、ch4），每个通道配备100 Bytes的RAM，当存满数据后停止数据采集并且相应通道的状态位产生报警信号。 5.数据分为8位串行输出，输出时钟由外部数据读取电路给出。 6.具备显示模块驱动功能。由SEL信号设置显示的通道，DISPLAY信号启动所选通道RAM中数值的显示过程。数值顺次显示一遍后显示结束，可以重新设定SEL的值选择下一个通道。模块数据线为8位，显示器件为4个8段LED。 7.数据采集模式如下：单通道采集（由SEL信号选择通道），多通道顺次采集（当前通道采满后转入下一通道），多通道并行采集（每通道依次采集一个数据）。模式由控制信号MODE选择，采集数据的总个数由NUM_COLLECT给出。 8.数据采集过程中不能读取，数据读取过程中不能采集-err
Platform: | Size: 5782528 | Author: pengfu | Hits:

[Other Embeded program] ShiftRegister

Description: Shift register verilog code
Platform: | Size: 1024 | Author: selcuk | Hits:

[VHDL-FPGA-Verilog] dual_port_ram

Description: 实现双口ram的读写功能，并含有测试文件，已经经过方针验证，很好用的-the writing and reading to the dual port ram ,good
Platform: | Size: 274432 | Author: zhangyan | Hits:

[Embeded-SCM Develop] c51

Description: 51单片机，USB，触摸，TFT,的等综合应用，高级别。（usb+flash+touch+tft+ram综合测试）-51 single-chip, USB, Touch, TFT, integrated applications (usb+ flash+ touch+ tft+ ram General Test)
Platform: | Size: 1505280 | Author: 程明 | Hits:

[VHDL-FPGA-Verilog] miffile

Description: 用matlab产生mif文件。(Altera的EDA软件，如maxplus，quartus等用到的初始化rom，ram等的文件格式)-Mif files generated by matlab. (Altera' s EDA software, such as maxplus, quartus used to initialize and so on rom, ram, such as the file format)
Platform: | Size: 1024 | Author: 何亮 | Hits:

[VHDL-FPGA-Verilog] hh

Description: 双口RAM的verilog描述 双口RAM的verilog描述-Dual-port RAM of the verilog description of dual-port RAM of the verilog description
Platform: | Size: 7168 | Author: 落木 | Hits:

[VHDL-FPGA-Verilog] HardCamera

Description: The objective of this project is to create a driver for a camera module (we used the OV7620). After taking the image with the camera, the driver will store into the external asynchronous RAM, and then send it to the computer through a serial cable
Platform: | Size: 5120 | Author: Joelmir J Lopes | Hits:

[Other] ADV7123_a

Description: adv7123 ram dac 10bit used always for hicolor fpga designs also soc systems
Platform: | Size: 309248 | Author: urga turg | Hits:

[VHDL-FPGA-Verilog] IDTContrl

Description: 该Verilog程序提供了一种控制IDT系列Ram的读写操作程序，每次读写750个16位的数。-The Verilog program control IDT provides a series of read and write operating procedures Ram, 750 each to read and write the number 16.
Platform: | Size: 1024 | Author: 刘进 | Hits:

[SCM] dual_ram

Description: FPGA和双端口RAM的DDS任意波形发生器的实现-FPGA and dual-port RAM of the DDS Arbitrary Waveform Generator
Platform: | Size: 513024 | Author: 刘磊 | Hits:

[VHDL-FPGA-Verilog] dds_easy

Description: 直接频率合成DDS模块的ise工程，可以直接下载，在Spartan3/Spartan3E上验证通过。该DDS模块可以产生双通道的不同频率的正弦波，也可以产生同频的任意相位差的相移波形。本模块累加器位数为32位，可以产生12位相位精度12位量化精度的正弦波。该设计例化一个Block Ram，为节省储存空间仅需要储存1/4周期的数据。根据需要，可以重新修改数据，改变波形。-DDS direct frequency synthesizer module ，ise project, can be directly downloaded through the Spartan3/Spartan3E and tested successfully. The DDS module can generate two-channel sine wave of different frequency, or produce the same frequency arbitrary waveform phase difference of the phase shift. There is a 32-bit accumulator to generate 12 bit phase-precision 12-bit quantization precision of the sine wave. Cases the design of a Block Ram, in order to save storage space need to store only 1/4 cycle of data. Necessary, can modify data, change the waveform.
Platform: | Size: 471040 | Author: 郭先生 | Hits:

[VHDL-FPGA-Verilog] bram_delay

Description: Verilog编写的代码，单口RAM用程序控制地址，而不是在仿真文件里面控制地址-Verilog code is written, single-port RAM with the process control address, rather than inside the control address of the simulation file
Platform: | Size: 1438720 | Author: niuniu | Hits:

[VHDL-FPGA-Verilog] rom

Description: 基于Verilog语言编写的各种只读存储器rom和随机存储器ram-Verilog language based on a variety of read-only memory rom and random access memory ram
Platform: | Size: 704512 | Author: 李辽原 | Hits:

[VHDL-FPGA-Verilog] dual_RAM

Description: vhdl语言编写的双口ram及testbench,模块可以在modelsim里进行时序和功能仿真。-vhdl language of the dual-port ram, and testbench, modules, conducted in the modelsim timing and functional simulation.
Platform: | Size: 1024 | Author: 易凯 | Hits:

[VHDL-FPGA-Verilog] x3cs400_uart

Description: 基于X3cS400的串口通讯程序，开发环境ISE7.0，使用verilog编写。可以使用串口调试助手在pc机上查看字符。-UART communication program based on X3CS400 FPGA， develop enviroment： ISE7.0，completed by verilog。 The result could be seen on the Uart debug assitant.
Platform: | Size: 569344 | Author: lingfeng | Hits:

[Other] rom_prf_gen

Description: 用ram存储顺序，用此方法也可以实现其他的顺序数据，代码用verilog编写-Ram memory with the order can be achieved using this method also the order of the other data, write code using verilog
Platform: | Size: 2048 | Author: zhm | Hits:

[VHDL-FPGA-Verilog] bubblesort1024ram

Description: 快速冒泡排序基于FPGA实现，有测试文件以及设计图，实现1024*32位数序的多数排序，突破传统是的REG类型少数排序，利用RAM，针对RAM中的无序数的地址调换，达到排序目的，仅供学习交流-Rapid bubble sort based on FPGA, there are test documents and design drawings to achieve 1024* 32-digit sequence of the majority of sorting, breaking tradition is a REG types of minority sorting, the use of RAM, the disorder for the RAM address of the number of exchange, to sort purpose, only to learn the exchange of.
Platform: | Size: 5120 | Author: 柳泽明 | Hits:
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